1. Field of the Invention
The present invention relates to a method of fabricating an isolation structure of a semiconductor device. More particularly, the present invention relates to a method of fabricating a trench isolation structure having sidewall oxide layers, each of a different thickness.
2. Description of the Related Art
As semiconductor devices become more highly integrated, isolation technologies for electrically isolating adjacent transistors become increasingly more important. Since conventional local oxidation of silicon (LOCOS) processes are not appropriate for semiconductor devices having a fine design rule of 0.5 xcexcm or less, trench isolation techniques are widely used to provide the necessary electrical isolation. In a typical trench isolation application, a trench is formed by etching an isolation area of a semiconductor substrate and then filled with a dielectric material to form an isolation layer.
A disadvantage of conventional trench isolation technology is that silicon lattice defects and damage may occur on an inner surface of the trench during a conventional dry etching process used in the forming of the trench. To reduce such silicon lattice defects and damage, a method can be used that forms a sidewall oxide layer by thermally oxidizing the inner surface of the trench. However, since the presence of the oxide layer can generate stress due to differences in thermal expansion coefficients between silicon oxide layers, a nitride liner is often deposited between a trench sidewall oxide layer and a silicon oxide layer. Such a nitride liner has an effect of improving the refresh characteristics of N-channel MOS transistors in dynamic random access memory (DRAM) devices, for example.
However, when the above process is used in the fabrication of a P-channel channel MOS transistor, hot electrons may be trapped in the nitride liner, thus deteriorating the electrical characteristics of the P-channel MOS transistor. In other words, hot electrons are generated due to an impact ionization and then are trapped in the nitride liner. Such hot electrons can create several problems, one of which is a formation of an abnormal conduction path to any device that is adjacent to the P-channel MOS transistor. This abnormal conduction path, which results from a particular distribution of electrical holes in the trench area, increases leakage current flowing between impurity areas of the two devices. Additionally, due to the hole accumulation around the trench, an effective channel length becomes shorter in any P-channel MOS transistor which is adjacent to the trench. As a result, a short-channel effect is increased, and the electrical characteristics of the P-channel transistor deteriorate.
The above electron/hole problems do not occur in an adjacent N-channel transistor, since it has an opposite conduction property. Specifically, any holes accumulating around the trench serve as an isolation area, and a majority of carriers are electrons. Thus, the effective channel length is not reduced in the N-channel MOS transistor.
In order to solve the above problems of the P-channel MOS transistor, a method of forming a thick sidewall oxide layer has been proposed. Specifically, a thick sidewall oxide layer may reduce the density of electrons trapped in a nitride liner. In the meantime, in the case of N-channel MOS transistors, a thick sidewall oxide layer deteriorates the refresh characteristics of the N-channel MOS transistors. Consequently, in a case where complementary-type MOS transistors, i.e., N-channel MOS transistors and P-channel MOS transistors, are formed in a substrate, the thickness of a sidewall oxide layer in the N-channel MOS transistor should be different from the thickness of a sidewall oxide layer in the P-channel MOS transistor.
It is a feature of an embodiment of the present invention to provide a method of forming a trench isolation structure having sidewall oxide layers each of different a thickness in an isolation area of an N-channel MOS transistor and in an isolation area of a P-channel MOS transistor to prevent holes from accumulating around a trench isolation area of the P-channel MOS transistor of complementary MOS transistors.
Accordingly, to provide the above feature, there is provided a method of fabricating a trench isolation structure, wherein a first trench in a first isolation area is separated from a second trench in a second isolation area, both trenches being included on a common semiconductor substrate, comprising: forming the first and second trenches; forming a nitrogen (N)-rich silicon layer on the sidewall surface of the second trench by implanting nitrogen into the second trench; forming an oxide layer having a first thickness on the sidewalls of the first trench and a having a second thickness on the sidewalls of the second trench via an oxidation process; forming a stress relief liner on the oxide layers of the first and second trenches; and filling the first and second trenches with a dielectric material.
Preferably, the formation of the first and second trenches includes: forming an etch stopping layer pattern on the semiconductor substrate to expose the first and second isolation areas; and forming the first and second trenches by etching the semiconductor substrate in the first and second isolation areas using the etch stopping layer pattern as an etch mask. The etch stopping layer pattern may be a stack layer pattern of a pad oxide layer and a silicon nitride layer. Preferably, the formation of a nitrogen (N)-rich silicon layer on the sidewall of the second trench includes: forming a mask layer pattern for exposing the second trench while covering the first trench; implanting nitrogen into the exposed second trench using the mask layer pattern as an implantation mask to form the nitrogen (N)-rich silicon layer; and removing the mask layer pattern. The mask layer pattern may be a photoresist layer. Implanting nitrogen into the second trench may be performed by an ion implantation process. Preferably, implantation energy and dosage in the ion implantation process are determined by the desired second thickness of the sidewall oxide layer of the second trench. Implanting nitrogen into the second trench may also be performed by a plasma nitridation process. It is preferable that the first isolation area delimits the P-channel channel MOS transistor area and the second isolation area delimits the N-channel channel MOS transistor area. The first thickness of the first sidewall oxide layer is preferably 100 to 300 xc3x85. The second thickness of the second sidewall oxide layer is preferably 20 to 100 xc3x85. The oxidation process for forming the first and second sidewall oxide layers is preferably a thermal oxidation process. The stress relief liner is preferably a nitride liner.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.